[all-commits] [llvm/llvm-project] f904d5: [PowerPC] Remaining KnownBits should be constant w...

[bzEq via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f904d50c29f23510cdbae0579085ae7ffebc1f63
      https://github.com/llvm/llvm-project/commit/f904d50c29f23510cdbae0579085ae7ffebc1f63
  Author: Kai Luo <lkail at cn.ibm.com>
  Date:   2020-12-30 (Wed, 30 Dec 2020)

  Changed paths:
    M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
    A llvm/test/CodeGen/PowerPC/pr48388.ll

  Log Message:
  -----------
  [PowerPC] Remaining KnownBits should be constant when performing non-sign comparison

In `PPCTargetLowering::DAGCombineTruncBoolExt`, when checking if it's correct to perform the transformation for non-sign comparison, as the comment says
```
      // This is neither a signed nor an unsigned comparison, just make sure
      // that the high bits are equal.
```
Origin check
```
      if (Op1Known.Zero != Op2Known.Zero || Op1Known.One != Op2Known.One)
        return SDValue();
```
is not strong enough. For example,
```
Op1Known = 111x000x;
Op2Known = 111x000x;
```
Bit 4, besides bit 0, is still unknown and affects the final result.

This patch fixes https://bugs.llvm.org/show_bug.cgi?id=48388.

Reviewed By: nemanjai, #powerpc

Differential Revision: https://reviews.llvm.org/D93092