[all-commits] [llvm/llvm-project] 6da003: [RISCV] Define vsext/vzext intrinsics.

[Zakk Chen via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 6da00336248ca725f5f817337e8486c234ace187
      https://github.com/llvm/llvm-project/commit/6da00336248ca725f5f817337e8486c234ace187
  Author: Zakk Chen <zakk.chen at sifive.com>
  Date:   2020-12-29 (Tue, 29 Dec 2020)

  Changed paths:
    M llvm/include/llvm/IR/IntrinsicsRISCV.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    A llvm/test/CodeGen/RISCV/rvv/vsext-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vsext-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vzext-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vzext-rv64.ll

  Log Message:
  -----------
  [RISCV] Define vsext/vzext intrinsics.

Define vsext/vzext intrinsics.and lower to V instructions.
Define new fraction register class fields in LMULInfo and a
NoReg to present invalid LMUL register classes.

Authored-by: ShihPo Hung <shihpo.hung at sifive.com>
Co-Authored-by: Zakk Chen <zakk.chen at sifive.com>

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D93893