[all-commits] [llvm/llvm-project] 58ce47: Fix DRR pattern when attributes and operands are i...

[Mehdi Amini via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 58ce477676c7bd9c6cee0c6d05f2708b4e178ff3
      https://github.com/llvm/llvm-project/commit/58ce477676c7bd9c6cee0c6d05f2708b4e178ff3
  Author: Mehdi Amini <joker.eph at gmail.com>
  Date:   2020-12-30 (Wed, 30 Dec 2020)

  Changed paths:
    M mlir/test/mlir-tblgen/rewriter-indexing.td
    M mlir/tools/mlir-tblgen/RewriterGen.cpp

  Log Message:
  -----------
  Fix DRR pattern when attributes and operands are interleaved and a dag subtree appears in the rewrite

This fixes an incorrect fatal error in TableGen. This code probably comes
from before attributes were allowed to interleave with operands in ODS.

Reviewed By: jpienaar

Differential Revision: https://reviews.llvm.org/D93915