[all-commits] [llvm/llvm-project] 79cbb0: [RISCV] Don't use tail agnostic policy on instruct...

Craig Topper via All-commits all-commits at lists.llvm.org
Tue Dec 29 10:39:32 PST 2020 

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 79cbb003c53009e5ca35b804bb7655dba97776e7
      https://github.com/llvm/llvm-project/commit/79cbb003c53009e5ca35b804bb7655dba97776e7
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2020-12-29 (Tue, 29 Dec 2020)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    M llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h
    M llvm/test/CodeGen/RISCV/rvv/vaadd-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vaadd-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vaaddu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vaaddu-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vadd-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vadd-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vand-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vand-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vasub-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vasub-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vasubu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vasubu-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vdiv-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vdiv-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vdivu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vdivu-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfadd-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfadd-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfdiv-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfdiv-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmacc-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmacc-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmadd-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmadd-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmax-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmax-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmin-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmin-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmsac-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmsac-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmsub-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmsub-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmul-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmul-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfnmacc-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfnmacc-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfnmadd-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfnmadd-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfnmsac-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfnmsac-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfnmsub-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfnmsub-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfrdiv-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfrdiv-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfrsub-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfrsub-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfsgnj-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfsgnj-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfsgnjn-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfsgnjn-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfsgnjx-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfsgnjx-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfslide1down-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfslide1down-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfsub-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfsub-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwadd-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwadd-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwmacc-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwmacc-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwmsac-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwmsac-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwmul-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwmul-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwnmacc-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwnmacc-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwnmsac-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwnmsac-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwsub-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwsub-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vid-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vid-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/viota-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/viota-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vle-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vle-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vleff-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vleff-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vlse-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vlse-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vlxe-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vlxe-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vmacc-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmacc-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vmadd-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmadd-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vmax-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmax-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vmaxu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmaxu-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vmfeq-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmfeq-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vmfge-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmfge-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vmfgt-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmfgt-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vmfle-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmfle-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vmflt-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmflt-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vmfne-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmfne-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vmin-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmin-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vminu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vminu-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsbf-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsbf-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vmseq-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmseq-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsgt-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsgt-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsif-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsif-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsle-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsle-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsleu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsleu-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vmslt-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmslt-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsltu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsltu-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsne-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsne-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsof-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsof-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vmul-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmul-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vmulh-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmulh-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vmulhsu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmulhsu-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vmulhu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmulhu-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vnclip-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vnclip-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vnclipu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vnclipu-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vnmsac-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vnmsac-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vnmsub-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vnmsub-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vnsra-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vnsra-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vnsrl-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vnsrl-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vor-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vor-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vrem-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vrem-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vremu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vremu-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vrgather-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vrgather-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vrsub-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vrsub-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vsadd-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vsadd-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vsaddu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vsaddu-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vslide1down-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vslide1down-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vslide1up-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vslidedown-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vslidedown-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vslideup-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vslideup-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vsll-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vsll-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vsmul-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vsmul-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vsra-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vsra-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vsrl-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vsrl-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vssra-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vssra-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vssrl-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vssrl-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vssub-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vssub-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vssubu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vssubu-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vsub-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vsub-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vwadd-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vwadd-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vwadd.w-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vwadd.w-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vwaddu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vwaddu-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vwaddu.w-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vwaddu.w-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vwmacc-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vwmacc-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vwmaccsu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vwmaccsu-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vwmaccu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vwmaccu-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vwmaccus-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vwmaccus-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vwmul-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vwmul-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vwmulsu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vwmulsu-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vwmulu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vwmulu-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vwsub-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vwsub-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vwsub.w-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vwsub.w-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vwsubu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vwsubu-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vxor-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vxor-rv64.ll

  Log Message:
  -----------
  [RISCV] Don't use tail agnostic policy on instructions where destination is tied to source

If the destination is tied, then user has some control of the
register used for input. They would have the ability to control
the value of any tail elements. By using tail agnostic we take
this option away from them.

Its not clear that the intrinsics are defined such that this isn't
supposed to work. And undisturbed is a valid implementation for agnostic
so code wouldn't even fail to work on all systems if we always used
agnostic.

The vcompress intrinsic is defined to require tail undisturbed so
at minimum we need this for that instruction or need to redefine
the intrinsic.

I've made an exception here for vmv.s.x/fmv.s.f and reduction
instructions which only write to element 0 regardless of the tail
policy. This allows us to keep the agnostic policy on those which
should allow better redundant vsetvli removal.

An enhancement would be to check for undef input and keep the
agnostic policy, but we don't have good test coverage for that yet.

Reviewed By: khchen

Differential Revision: https://reviews.llvm.org/D93878

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