[all-commits] [llvm/llvm-project] 2ae760: [RISCV] Add earlyclobber of destination register t...

[Craig Topper via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 2ae760e27e6ad27cf16603e2fa805bec45efc68c
      https://github.com/llvm/llvm-project/commit/2ae760e27e6ad27cf16603e2fa805bec45efc68c
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2020-12-29 (Tue, 29 Dec 2020)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    M llvm/test/CodeGen/RISCV/rvv/vmsbf-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsbf-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsif-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsif-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsof-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsof-rv64.ll

  Log Message:
  -----------
  [RISCV] Add earlyclobber of destination register to vmsbf.m/vmsif.m/vmsof.m instructions

The spec for these instructions include this note. "The destination register
cannot overlap either the source register or the mask register ('v0') if the
instruction is masked." So we need earlyclobber to enforce this constraint.

I've regenerated the tests with update_llc_test_checks.py to show the
effects of the earlyclobber.

Reviewed By: khchen, frasercrmck

Differential Revision: https://reviews.llvm.org/D93867