[all-commits] [llvm/llvm-project] f3f9ce: [RISCV] Define vmclr.m/vmset.m intrinsics.

[Zakk Chen via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: f3f9ce3b7948b250bc532818ed76a64cea8b6fbe
      https://github.com/llvm/llvm-project/commit/f3f9ce3b7948b250bc532818ed76a64cea8b6fbe
  Author: Zakk Chen <zakk.chen at sifive.com>
  Date:   2020-12-28 (Mon, 28 Dec 2020)

  Changed paths:
    M llvm/include/llvm/IR/IntrinsicsRISCV.td
    M llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    A llvm/test/CodeGen/RISCV/rvv/vmclr-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vmclr-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vmset-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vmset-rv64.ll

  Log Message:
  -----------
  [RISCV] Define vmclr.m/vmset.m intrinsics.

Define vmclr.m/vmset.m intrinsics and lower to vmxor.mm/vmxnor.mm.

Ideally all rvv pseudo instructions could be implemented in C header,
but those two instructions don't take an input, codegen can not guarantee
that the source register becomes the same as the destination.

We expand pseduo-v-inst into corresponding v-inst in
RISCVExpandPseudoInsts pass.

Reviewed By: craig.topper, frasercrmck

Differential Revision: https://reviews.llvm.org/D93849