[all-commits] [llvm/llvm-project] b90e2d: [RISCV] Use tail agnostic policy for vsetvli instr...

[Craig Topper via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: b90e2d850e780d290b554963db1cd264625a73a4
      https://github.com/llvm/llvm-project/commit/b90e2d850e780d290b554963db1cd264625a73a4
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2020-12-10 (Thu, 10 Dec 2020)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/add-vsetvli-gpr.mir
    M llvm/test/CodeGen/RISCV/rvv/add-vsetvli-vlmax.ll
    M llvm/test/CodeGen/RISCV/rvv/load-add-store-16.ll
    M llvm/test/CodeGen/RISCV/rvv/load-add-store-32.ll
    M llvm/test/CodeGen/RISCV/rvv/load-add-store-64.ll
    M llvm/test/CodeGen/RISCV/rvv/load-add-store-8.ll

  Log Message:
  -----------
  [RISCV] Use tail agnostic policy for vsetvli instruction emitted in the custom inserter

The compiler is making no effort to preserve upper elements. To do so would require another source operand tied with the destination and a different intrinsic interface to give control of this source to the programmer.

This patch changes the tail policy to agnostic so that the CPU doesn't need to make an effort to preserve them.

This is consistent with the RVV intrinsic spec here https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#configuration-setting

Differential Revision: https://reviews.llvm.org/D93080