[all-commits] [llvm/llvm-project] 6ee22c: [RISCV] Add tests for existing (rotr (bswap X), (i...

[Craig Topper via All-commits]

  Branch: refs/heads/temp-test-main
  Home:   https://github.com/llvm/llvm-project
  Commit: 6ee22ca6ceb71661e8dbc296b471ace0614c07e5
      https://github.com/llvm/llvm-project/commit/6ee22ca6ceb71661e8dbc296b471ace0614c07e5
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2020-11-27 (Fri, 27 Nov 2020)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoB.td
    M llvm/test/CodeGen/RISCV/rv32Zbp.ll
    M llvm/test/CodeGen/RISCV/rv64Zbp.ll

  Log Message:
  -----------
  [RISCV] Add tests for existing (rotr (bswap X), (i32 16))->grevi pattern for RV32. Extend same pattern to rotl and GREVIW.

Not sure why bswap was treated specially. This also applies to bitreverse
or generic grevi. We can improve this in future patches.
For now I just wanted to get the consistency and the test coverage
as I plan to make some other changes around bswap.