[all-commits] [llvm/llvm-project] f325b4: [RISCV] Replace sexti32/zexti32 in isel patterns w...

[Craig Topper via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: f325b4bbceb5e680e64532dd018b3c0a36d1b01a
      https://github.com/llvm/llvm-project/commit/f325b4bbceb5e680e64532dd018b3c0a36d1b01a
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2020-11-27 (Fri, 27 Nov 2020)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoD.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoF.td

  Log Message:
  -----------
  [RISCV] Replace sexti32/zexti32 in isel patterns where only one part of their PatFrags can match. NFCI

We had an zexti32 after a sign_extend_inreg. The AND X, 0xffffffff
part of the zexti32 should never occur since SimplifyDemandedBits
from the sign_extend_inreg would have removed it.

We also had sexti32 as the root node of a pattern, but SelectionDAGISel
matches assertsext early before the tablegen based patterns are
evaluated.


  Commit: fa0f01a3c0e1bdc1a0b4e1188445335184eae03c
      https://github.com/llvm/llvm-project/commit/fa0f01a3c0e1bdc1a0b4e1188445335184eae03c
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2020-11-27 (Fri, 27 Nov 2020)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
    M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
    M llvm/test/CodeGen/RISCV/rv64Zbb.ll

  Log Message:
  -----------
  [RISCV][LegalizeTypes] Teach type legalizer that it can promote UMIN/UMAX using SExtPromotedInteger if that's better for the target.

If Sext is cheaper than Zext for a target, we can use that to promote the operands of UMIN/UMAX. Using sext just makes numbers with the sign bit set even larger when treated as an unsigned number and it has no effect on number without the sign bit set. So the relative order doesn't change. This is similar to what we already do for promoting SETCC.

This is helpful on RISCV where i32 arguments are sign extended on RV64 and many instructions are able to produce results with 33 sign bits.

Differential Revision: https://reviews.llvm.org/D92128


Compare: https://github.com/llvm/llvm-project/compare/b7bde0e4f3d2...fa0f01a3c0e1