[all-commits] [llvm/llvm-project] c46284: [Hexagon] Add HVX support for ISD::SMAX/SMIN/UMAX/...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/temp-test-main
  Home:   https://github.com/llvm/llvm-project
  Commit: c4628460b74bcdc34041cd11a8959ca336637ee2
      https://github.com/llvm/llvm-project/commit/c4628460b74bcdc34041cd11a8959ca336637ee2
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2020-11-27 (Fri, 27 Nov 2020)

  Changed paths:
    M llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
    M llvm/lib/Target/Hexagon/HexagonPatternsHVX.td
    M llvm/test/CodeGen/Hexagon/autohvx/minmax-128b.ll
    M llvm/test/CodeGen/Hexagon/autohvx/minmax-64b.ll

  Log Message:
  -----------
  [Hexagon] Add HVX support for ISD::SMAX/SMIN/UMAX/UMIN instead of custom dag patterns

Followup to D92112 now that I've learnt about HVX type splitting.

This is some necessary cleanup work for min/max ops to eventually help us move the add/sub sat patterns into DAGCombine - D91876.

Differential Revision: https://reviews.llvm.org/D92169