[all-commits] [llvm/llvm-project] 8fb8fb: [RISCV] Add test cases for missed opportunities to...

[Craig Topper via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 8fb8fb2c607794fe4cde69713f2fa556f613dab1
      https://github.com/llvm/llvm-project/commit/8fb8fb2c607794fe4cde69713f2fa556f613dab1
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2020-11-26 (Thu, 26 Nov 2020)

  Changed paths:
    M llvm/test/CodeGen/RISCV/rv64Zbs.ll

  Log Message:
  -----------
  [RISCV] Add test cases for missed opportunities to use sbsetw/sbclrw/sbinvw when the result isn't known to be sign extended.

If the input isn't sign extended, but the output of the or/xor/and
is used by a sign_inreg we can still use sbsetw/sbclrw/sbinvw.


  Commit: d9500c2e230e9cc68d3d647864fa824cc3c06b3f
      https://github.com/llvm/llvm-project/commit/d9500c2e230e9cc68d3d647864fa824cc3c06b3f
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2020-11-26 (Thu, 26 Nov 2020)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoB.td
    M llvm/test/CodeGen/RISCV/rv64Zbs.ll

  Log Message:
  -----------
  [RISCV] Add isel patterns for sbsetw/sbclrw/sbinvw with sext_inreg as the root.

This handles cases were the input isn't known to be sign extended.


Compare: https://github.com/llvm/llvm-project/compare/d8ffb1f6a757...d9500c2e230e