[all-commits] [llvm/llvm-project] 2254e0: [RISCV] Add isel pattern to match (i64 (sra (shl X...

[Craig Topper via All-commits]

  Branch: refs/heads/temp-test-main
  Home:   https://github.com/llvm/llvm-project
  Commit: 2254e014a9019bf17c3f5cb27c1dc40ca0f2ffce
      https://github.com/llvm/llvm-project/commit/2254e014a9019bf17c3f5cb27c1dc40ca0f2ffce
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2020-11-25 (Wed, 25 Nov 2020)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfo.td
    M llvm/test/CodeGen/RISCV/alu64.ll

  Log Message:
  -----------
  [RISCV] Add isel pattern to match (i64 (sra (shl X, 32), C)) to SRAIW if C > 32.