[all-commits] [llvm/llvm-project] 751b0d: [RISCV] Make SMIN/SMAX/UMIN/UMAX legal with Zbb ex...

[Craig Topper via All-commits]

  Branch: refs/heads/temp-test-main
  Home:   https://github.com/llvm/llvm-project
  Commit: 751b0d970e757aef055fb6e1a981a7c44185aa80
      https://github.com/llvm/llvm-project/commit/751b0d970e757aef055fb6e1a981a7c44185aa80
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2020-11-25 (Wed, 25 Nov 2020)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoB.td
    M llvm/test/CodeGen/RISCV/rv32Zbb.ll
    M llvm/test/CodeGen/RISCV/rv64Zbb.ll

  Log Message:
  -----------
  [RISCV] Make SMIN/SMAX/UMIN/UMAX legal with Zbb extension.

This is the logically correct thing to do. But it generates worse
code for i32 umin/umax on the rv64 due to type legalize requesting
zext even though the arguments are sext. Maybe we can teach type
legalizer to use sext for umin/umax for RISCV.

It's also producing possibly worse code on i64 on RV32 since we
still end up with selects that become branches. But this seems
like something we could improve in type legalization or DAG combine.

Hopefully this makes D92095 work for RISCV with Zbb.


  Commit: bd0527f3942d2045be4e3a6b5e7eb98752bf7200
      https://github.com/llvm/llvm-project/commit/bd0527f3942d2045be4e3a6b5e7eb98752bf7200
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2020-11-25 (Wed, 25 Nov 2020)

  Changed paths:
    M llvm/test/CodeGen/RISCV/rv32Zbb.ll
    M llvm/test/CodeGen/RISCV/rv64Zbb.ll

  Log Message:
  -----------
  [RISCV] Add test cases to check that we use (smax X, (neg X)) for abs with Zbb extension.


Compare: https://github.com/llvm/llvm-project/compare/a78aaa1ad512...bd0527f3942d