[all-commits] [llvm/llvm-project] a01563: [Hexagon] Add support for ISD::SMAX/SMIN/UMAX/UMIN...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: a0156356296b54dc071405332a517695b1881bc1
      https://github.com/llvm/llvm-project/commit/a0156356296b54dc071405332a517695b1881bc1
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2020-11-25 (Wed, 25 Nov 2020)

  Changed paths:
    M llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
    M llvm/lib/Target/Hexagon/HexagonPatterns.td
    M llvm/test/CodeGen/Hexagon/isel-minmax-v64bit.ll

  Log Message:
  -----------
  [Hexagon] Add support for ISD::SMAX/SMIN/UMAX/UMIN instead of custom dag patterns

This should handle the basic integer min/max handling - the HVX ops are still TODO.

This is some necessary cleanup work for min/max ops to eventually help us move the add/sub sat patterns into DAGCombine - D91876.

Differential Revision: https://reviews.llvm.org/D92112