[all-commits] [llvm/llvm-project] dfbb5a: [mlir] Remove SameOperandsAndResultShape when redu...

[Sean Silva via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: dfbb5a087e20ea1c14300eef600e52360320b390
      https://github.com/llvm/llvm-project/commit/dfbb5a087e20ea1c14300eef600e52360320b390
  Author: Sean Silva <silvasean at google.com>
  Date:   2020-11-24 (Tue, 24 Nov 2020)

  Changed paths:
    M mlir/include/mlir/Dialect/StandardOps/IR/Ops.td
    M mlir/test/IR/invalid-ops.mlir

  Log Message:
  -----------
  [mlir] Remove SameOperandsAndResultShape when redundant with ElementwiseMappable

SameOperandsAndResultShape and ElementwiseMappable have similar
verification, but in general neither is strictly redundant with the
other.

Examples:
- SameOperandsAndResultShape allows
  `"foo"(%0) : tensor<2xf32> -> tensor<?xf32> but ElementwiseMappable
  does not.
- ElementwiseMappable allows
  `select %scalar_pred, %true_tensor, %false_tensor` but
  SameOperandsAndResultShape does not.

SameOperandsAndResultShape is redundant with ElementwiseMappable when
we can prove that the mixed scalar/non-scalar case cannot happen. In
those situations, `ElementwiseMappable & SameOperandsAndResultShape ==
ElementwiseMappable`:
- Ops with 1 operand: the case of mixed scalar and non-scalar operands
  cannot happen since there is only one operand.
- When SameTypeOperands is also present, the mixed scalar/non-scalar
  operand case cannot happen.

Differential Revision: https://reviews.llvm.org/D91396