[all-commits] [llvm/llvm-project] bb1341: [libunwind] Multiple preprocessor fixes on PowerPC*

[Brandon Bergren via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: bb1341161478dc589893cda9f808e5f5b859b5ae
      https://github.com/llvm/llvm-project/commit/bb1341161478dc589893cda9f808e5f5b859b5ae
  Author: Brandon Bergren <git at bdragon.rtk0.net>
  Date:   2020-11-23 (Mon, 23 Nov 2020)

  Changed paths:
    M libunwind/src/Registers.hpp
    M libunwind/src/UnwindRegistersRestore.S
    M libunwind/src/UnwindRegistersSave.S
    M libunwind/src/assembly.h
    M libunwind/src/config.h

  Log Message:
  -----------
  [libunwind] Multiple preprocessor fixes on PowerPC*

* Remove misnamed `PPC64_HAS_VMX` in preference of directly checking `defined(__VSX__)`.

libunwind was using "VMX" to mean "VSX". "VMX" is just another name for Altivec, while "VSX" is the vector-scalar extensions first used in POWER7. Exposing a "PPC64_HAS_VMX" define was misleading and incorrect.

* Add `defined(__ALTIVEC__)` guards around vector register operations to fix non-altivec CPUS such as the e5500.

When compiling for certain Book-E processors such as the e5500, we want to skip vector save/restore, as the Altivec registers are illegal on non-Altivec implementations.

* Add `!defined(__NO_FPRS__)` guards around traditional floating-point save/restore.

When compiling for powerpcspe, we cannot access floating point registers, as there aren't any. (The SPE on e500v2 is a 64-bit extension of the GPRs, and it doesn't have the normal floating-point registers at all.)
This fixes building for powerpcspe, although no actual handling for SPE save/restore is written yet.

Reviewed By: MaskRay, #libunwind, compnerd

Differential Revision: https://reviews.llvm.org/D91906