[all-commits] [llvm/llvm-project] 4252f7: [SelectionDAG][ARM][AArch64][Hexagon][RISCV][X86] ...
Craig Topper via All-commits
all-commits at lists.llvm.org
Mon Nov 23 10:35:17 PST 2020
Branch: refs/heads/temp-test-main
Home: https://github.com/llvm/llvm-project
Commit: 4252f7773a5b98b825d17e5f77c7d349cb2fb7c7
https://github.com/llvm/llvm-project/commit/4252f7773a5b98b825d17e5f77c7d349cb2fb7c7
Author: Craig Topper <craig.topper at sifive.com>
Date: 2020-11-23 (Mon, 23 Nov 2020)
Changed paths:
M llvm/include/llvm/Target/TargetSelectionDAG.td
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/ARM/ARMInstrMVE.td
M llvm/lib/Target/ARM/ARMInstrVFP.td
M llvm/lib/Target/Hexagon/HexagonPatterns.td
M llvm/lib/Target/RISCV/RISCVInstrInfoD.td
M llvm/lib/Target/RISCV/RISCVInstrInfoF.td
M llvm/lib/Target/X86/X86InstrAVX512.td
M llvm/lib/Target/X86/X86InstrFMA.td
M llvm/lib/Target/X86/X86InstrFragmentsSIMD.td
M llvm/test/CodeGen/AArch64/GlobalISel/select-with-no-legality-check.mir
M llvm/test/CodeGen/AArch64/arm64-vmul.ll
M llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir
M llvm/test/CodeGen/ARM/GlobalISel/select-pr35926.mir
M llvm/test/CodeGen/ARM/fp16-fusedMAC.ll
M llvm/test/CodeGen/RISCV/double-arith.ll
M llvm/test/CodeGen/RISCV/float-arith.ll
M llvm/test/CodeGen/Thumb2/mve-float32regloops.ll
M llvm/test/CodeGen/Thumb2/mve-fma-loops.ll
M llvm/test/CodeGen/Thumb2/mve-intrinsics/ternary.ll
Log Message:
-----------
[SelectionDAG][ARM][AArch64][Hexagon][RISCV][X86] Add SDNPCommutative to fma and fmad nodes in tablegen. Remove explicit commuted patterns from targets.
X86 was already specially marking fma as commutable which allowed
tablegen to autogenerate commuted patterns. This moves it to the target
independent definition and fix up the targets to remove now
unneeded patterns.
Unfortunately, the tests change because the commuted version of
the patterns are generating operands in a different than the
explicit patterns.
Differential Revision: https://reviews.llvm.org/D91842
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