[all-commits] [llvm/llvm-project] 44cd03: [RISCV] Use register class VR for V instruction op...

[Kai Wang via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 44cd03ad041e136b5fb1f512f470b1bfe1c49aad
      https://github.com/llvm/llvm-project/commit/44cd03ad041e136b5fb1f512f470b1bfe1c49aad
  Author: Hsiangkai Wang <kai.wang at sifive.com>
  Date:   2020-11-19 (Thu, 19 Nov 2020)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoV.td
    M llvm/test/MC/RISCV/rvv/invalid.s

  Log Message:
  -----------
  [RISCV] Use register class VR for V instruction operands directly.

@tangxingxin1008 found a bug that regard vadd.vv v1, v3, a0 as a valid V
instruction. We should remove the VRegAsmOperand operand class and use
VR register class directly.

Patched by: tangxingxin1008, Hsiangkai
Differential Revision: https://reviews.llvm.org/D91712