[all-commits] [llvm/llvm-project] adccc0: [X86] Add X86ISD opcodes for the Key Locker AESENC...

[topperc via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: adccc0bfa301005367d6b89a3aacc07ef0166e64
      https://github.com/llvm/llvm-project/commit/adccc0bfa301005367d6b89a3aacc07ef0166e64
  Author: Craig Topper <craig.topper at intel.com>
  Date:   2020-10-03 (Sat, 03 Oct 2020)

  Changed paths:
    M llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/lib/Target/X86/X86ISelLowering.h
    M llvm/lib/Target/X86/X86InstrInfo.td
    M llvm/lib/Target/X86/X86InstrKL.td
    M llvm/test/CodeGen/X86/keylocker-intrinsics.ll

  Log Message:
  -----------
  [X86] Add X86ISD opcodes for the Key Locker AESENC*KL and AESDEC*KL instructions

Instead of emitting MachineSDNodes during lowering, emit X86ISD
opcodes. These opcodes will either be selected by tablegen
patterns or custom selection code.

Emitting MachineSDNodes during lowering is uncommon so this makes
things more consistent. It also allows selectAddr to be called to
perform address matching during instruction selection.

I had trouble getting tablegen to accept XMM0-XMM7 as results in
an isel pattern for the WIDE instructions so I had to use custom
instruction selection.