[all-commits] [llvm/llvm-project] 067add: [RISCV] Support vmsge.vx and vmsgeu.vx pseudo inst...

[Kai Wang via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 067add7b5fd22c879bd2bbf5d55f4fb9b63047bf
      https://github.com/llvm/llvm-project/commit/067add7b5fd22c879bd2bbf5d55f4fb9b63047bf
  Author: Hsiangkai Wang <kai.wang at sifive.com>
  Date:   2020-10-02 (Fri, 02 Oct 2020)

  Changed paths:
    M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoV.td
    M llvm/lib/Target/RISCV/RISCVRegisterInfo.td
    M llvm/test/MC/RISCV/rvv/compare.s
    M llvm/test/MC/RISCV/rvv/invalid.s

  Log Message:
  -----------
  [RISCV] Support vmsge.vx and vmsgeu.vx pseudo instructions in RVV.

Implement vmsge{u}.vx pseudo instruction.

According to RISC-V V specification, there are different scenarios for this
pseudo instruction. I list them below.

unmasked va >= x

  pseudoinstruction: vmsge{u}.vx vd, va, x
  expansion: vmslt{u}.vx vd, va, x; vmnand.mm vd, vd, vd

masked va >= x, vd != v0

  pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t
  expansion: vmslt{u}.vx vd, va, x, v0.t; vmxor.mm vd, vd, v0

masked va >= x, vd == v0

  pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t, vt
  expansion: vmslt{u}.vx vt, va, x;  vmandnot.mm vd, vd, vt

Use pseudo instruction to model vmsge{u}.vx. The pseudo instruction will convert
to different expansion according to the condition.

Differential Revision: https://reviews.llvm.org/D84732