[all-commits] [llvm/llvm-project] c4690b: [PowerPC] Put the CR field in low bits of GRC duri...

[Esme via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: c4690b007743d2f564bc1156fdbdbcaad2adddcc
      https://github.com/llvm/llvm-project/commit/c4690b007743d2f564bc1156fdbdbcaad2adddcc
  Author: Esme-Yi <esme.yi at ibm.com>
  Date:   2020-10-02 (Fri, 02 Oct 2020)

  Changed paths:
    M llvm/lib/Target/PowerPC/PPCInstrHTM.td
    M llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
    M llvm/test/CodeGen/PowerPC/htm-ttest.ll

  Log Message:
  -----------
  [PowerPC] Put the CR field in low bits of GRC during copying CRRC to GRC.

Summary: How we copying the CRRC to GRC is using a single MFOCRF to copy the contents of CR field n (CR bits 4×n+32:4×n+35) into bits 4×n+32:4×n+35 of register GRC. That’s not correct because we expect the value of destination register equals to source so we have to put the the contents of CR field in the lowest 4 bits. This patch adds a RLWINM after MFOCRF to achieve that.
The problem came up when adding builtins for xvtdivdp, xvtdivsp, xvtsqrtdp, xvtsqrtsp, as posted in D88278. We need to move the outputs (in CR register) to GRC. However outputs of these instructions may not in a fixed CR# register, so we can’t directly add a rotation instruction in the .td patterns, but need to wait until the CR register is determined. Then we confirmed this should be a bug in POST-RA PSEUDO PASS.

Reviewed By: nemanjai, shchenz

Differential Revision: https://reviews.llvm.org/D88274