[all-commits] [llvm/llvm-project] e96289: [mlir] [VectorOps] Relaxed restrictions on vector....

[Aart Bik via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: e9628955f5e965b0a60b8df3c731fc6bfa87ad20
      https://github.com/llvm/llvm-project/commit/e9628955f5e965b0a60b8df3c731fc6bfa87ad20
  Author: Aart Bik <ajcbik at google.com>
  Date:   2020-09-28 (Mon, 28 Sep 2020)

  Changed paths:
    A mlir/integration_test/Dialect/Vector/CPU/test-reductions-i4.mlir
    A mlir/integration_test/Dialect/Vector/CPU/test-reductions-si4.mlir
    A mlir/integration_test/Dialect/Vector/CPU/test-reductions-ui4.mlir
    M mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp
    M mlir/lib/Dialect/Vector/VectorOps.cpp

  Log Message:
  -----------
  [mlir] [VectorOps] Relaxed restrictions on vector.reduction types even more

Recently, restrictions on vector reductions were made more relaxed by
accepting any width signless integer and floating-point. This CL relaxes
the restriction even more by including unsigned and signed integers.

Reviewed By: bkramer

Differential Revision: https://reviews.llvm.org/D88442