[all-commits] [llvm/llvm-project] 015691: [PowerPC] Legalize v256i1 and v512i1 and implement...

[bsaleil via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 0156914275be5b07155ecefe4dc2d58588265abc
      https://github.com/llvm/llvm-project/commit/0156914275be5b07155ecefe4dc2d58588265abc
  Author: Baptiste Saleil <baptiste.saleil at ibm.com>
  Date:   2020-09-28 (Mon, 28 Sep 2020)

  Changed paths:
    M clang/lib/Basic/Targets/PPC.h
    M clang/test/CodeGen/target-data.c
    M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
    M llvm/lib/Target/PowerPC/PPCISelLowering.h
    M llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
    M llvm/lib/Target/PowerPC/PPCInstrPrefix.td
    M llvm/lib/Target/PowerPC/PPCRegisterInfo.td
    M llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
    A llvm/test/CodeGen/PowerPC/mma-acc-memops.ll

  Log Message:
  -----------
  [PowerPC] Legalize v256i1 and v512i1 and implement load and store of these types

This patch legalizes the v256i1 and v512i1 types that will be used for MMA.

It implements loads and stores of these types.
v256i1 is a pair of VSX registers, so for this type, we load/store the two
underlying registers. v512i1 is used for MMA accumulators. So in addition to
loading and storing the 4 associated VSX registers, we generate instructions to
prime (copy the VSX registers to the accumulator) after loading and unprime
(copy the accumulator back to the VSX registers) before storing.

This patch also adds the UACC register class that is necessary to implement the
loads and stores. This class represents accumulator in their unprimed form and
allow the distinction between primed and unprimed accumulators to avoid invalid
copies of the VSX registers associated with primed accumulators.

Differential Revision: https://reviews.llvm.org/D84968