[all-commits] [llvm/llvm-project] 331dcc: [PowerPC] Implemented Vector Load with Zero and Si...

[Conanap via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 331dcc43eac28b8e659f928fd1f1ce7fd091e1e3
      https://github.com/llvm/llvm-project/commit/331dcc43eac28b8e659f928fd1f1ce7fd091e1e3
  Author: Albion Fung <albionapc at gmail.com>
  Date:   2020-08-28 (Fri, 28 Aug 2020)

  Changed paths:
    M clang/lib/Headers/altivec.h
    M clang/test/CodeGen/builtins-ppc-p10vector.c
    M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
    M llvm/lib/Target/PowerPC/PPCISelLowering.h
    M llvm/lib/Target/PowerPC/PPCInstrPrefix.td
    M llvm/test/CodeGen/PowerPC/builtins-ppc-p10vsx.ll

  Log Message:
  -----------
  [PowerPC] Implemented Vector Load with Zero and Signed Extend Builtins

This patch implements the builtins for Vector Load with Zero and Signed Extend Builtins (lxvr_x for b, h, w, d), and adds the appropriate test cases for these builtins. The builtins utilize the vector load instructions itnroduced with ISA 3.1.

Differential Revision: 	https://reviews.llvm.org/D82502#inline-797941