[all-commits] [llvm/llvm-project] 0015b8: [SVE] Add ISEL patterns for predicated shifts by a...

[paulwalker-arm via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 0015b8db8e5e4d8367578eae3bb71ce833de9d33
      https://github.com/llvm/llvm-project/commit/0015b8db8e5e4d8367578eae3bb71ce833de9d33
  Author: Paul Walker <paul.walker at arm.com>
  Date:   2020-08-20 (Thu, 20 Aug 2020)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
    M llvm/lib/Target/AArch64/SVEInstrFormats.td
    M llvm/test/CodeGen/AArch64/sve-fixed-length-int-immediates.ll

  Log Message:
  -----------
  [SVE] Add ISEL patterns for predicated shifts by an immediate.

For scalable vector shifts the prediacte is typically all active,
which gets selected to an unpredicated shift by immediate.  When
code generating for fixed length vectors the predicate is based
on the vector length and so additional patterns are required to
make use of SVE's predicated shift by immediate instructions.

Differential Revision: https://reviews.llvm.org/D86204