[all-commits] [llvm/llvm-project] 7ff957: [AArch64][GlobalISel] Select XRO addressing mode w...

[Jessica Paquette via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 7ff9575594d001f0c514f35add36eaf7b6c5e12f
      https://github.com/llvm/llvm-project/commit/7ff9575594d001f0c514f35add36eaf7b6c5e12f
  Author: Jessica Paquette <jpaquette at apple.com>
  Date:   2020-07-29 (Wed, 29 Jul 2020)

  Changed paths:
    M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
    A llvm/test/CodeGen/AArch64/GlobalISel/xro-addressing-mode-constant.mir

  Log Message:
  -----------
  [AArch64][GlobalISel] Select XRO addressing mode with wide immediates

Port the wide immediate case from AArch64DAGToDAGISel::SelectAddrModeXRO.

If we have a wide immediate which can't be represented in an add, we can end up
with code like this:

```
mov  x0, imm
add x1, base, x0
ldr  x2, [x1, 0]
```

If we use the [base, xN] addressing mode instead, we can produce this:

```
mov  x0, imm
ldr  x2, [base, x0]
```

This saves 0.4% code size on 7zip at -O3, and gives a geomean code size
improvement of 0.1% on CTMark.

Differential Revision: https://reviews.llvm.org/D84784