[all-commits] [llvm/llvm-project] 766cb6: AMDGPU: Relax restriction on folding immediates in...

[Matt Arsenault via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 766cb615a3b96025192707f4670cdf171da84034
      https://github.com/llvm/llvm-project/commit/766cb615a3b96025192707f4670cdf171da84034
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2020-07-29 (Wed, 29 Jul 2020)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.kernarg.segment.ptr.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/zextload.ll
    M llvm/test/CodeGen/AMDGPU/fold-imm-copy.mir

  Log Message:
  -----------
  AMDGPU: Relax restriction on folding immediates into physregs

I never completed the work on the patches referenced by
f8bf7d7f42f28fa18144091022236208e199f331, but this was intended to
avoid folding immediate writes into m0 which the coalescer doesn't
understand very well. Relax this to allow simple SGPR immediates to
fold directly into VGPR copies. This pattern shows up routinely in
current GlobalISel code since nothing is smart enough to emit VGPR
constants yet.