[all-commits] [llvm/llvm-project] 6bba95: [X86] Change the scheduler model for 'pentium4' to...

[topperc via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 6bba95831e480656124a5fbcd84f4f2a31e6c0b6
      https://github.com/llvm/llvm-project/commit/6bba95831e480656124a5fbcd84f4f2a31e6c0b6
  Author: Craig Topper <craig.topper at intel.com>
  Date:   2020-07-16 (Thu, 16 Jul 2020)

  Changed paths:
    M llvm/lib/Target/X86/X86.td
    M llvm/test/CodeGen/X86/cfguard-x86-vectorcall.ll
    M llvm/test/CodeGen/X86/cmov-fp.ll
    M llvm/test/CodeGen/X86/post-ra-sched.ll
    M llvm/test/CodeGen/X86/pr34088.ll
    M llvm/test/CodeGen/X86/pr40539.ll
    M llvm/test/DebugInfo/COFF/fpo-stack-protect.ll

  Log Message:
  -----------
  [X86] Change the scheduler model for 'pentium4' to SandyBridgeModel.

I meant to do this in D83913, but missed it while updating the
feature list.

Interestingly I think this is disabling the postRA scheduler. But
it does match our default 64-bit behavior.

Reviewed By: echristo

Differential Revision: https://reviews.llvm.org/D83996