[all-commits] [llvm/llvm-project] 146d35: [ARM] CSEL generation

[David Green via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 146d35b6eeb5b360217d2f14a18c87b1a0aca77e
      https://github.com/llvm/llvm-project/commit/146d35b6eeb5b360217d2f14a18c87b1a0aca77e
  Author: David Green <david.green at arm.com>
  Date:   2020-07-16 (Thu, 16 Jul 2020)

  Changed paths:
    M llvm/lib/Target/ARM/ARMInstrThumb2.td
    M llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
    M llvm/lib/Target/ARM/Thumb2InstrInfo.h
    M llvm/test/CodeGen/Thumb2/csel.ll
    M llvm/test/CodeGen/Thumb2/float-ops.ll
    M llvm/test/CodeGen/Thumb2/mve-abs.ll
    M llvm/test/CodeGen/Thumb2/mve-satmul-loops.ll
    M llvm/test/CodeGen/Thumb2/mve-vecreduce-loops.ll
    M llvm/test/CodeGen/Thumb2/mve-vmaxv.ll

  Log Message:
  -----------
  [ARM] CSEL generation

This adds a peephole optimisation to turn a t2MOVccr that could not be
folded into any other instruction into a CSEL on 8.1-m. The t2MOVccr
would usually be expanded into a conditional mov, that becomes an IT;
MOV pair. We can instead generate a CSEL instruction, which can
potentially be smaller and allows better register allocation freedom,
which can help reduce codesize. Performance is more variable and may
depend on the micrarchitecture details, but initial results look good.
If we need to control this per-cpu, we can add a subtarget feature as we
need it.

Original patch by David Penry.

Differential Revision: https://reviews.llvm.org/D83566