[all-commits] [llvm/llvm-project] 2762da: [SVE][CodeGen] Legalisation of masked loads and st...

[kmclaughlin-arm via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 2762da0a16a763654254e3320a3f46be2bb742b4
      https://github.com/llvm/llvm-project/commit/2762da0a16a763654254e3320a3f46be2bb742b4
  Author: Kerry McLaughlin <kerry.mclaughlin at arm.com>
  Date:   2020-07-16 (Thu, 16 Jul 2020)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
    M llvm/test/CodeGen/AArch64/sve-split-load.ll
    M llvm/test/CodeGen/AArch64/sve-split-store.ll

  Log Message:
  -----------
  [SVE][CodeGen] Legalisation of masked loads and stores

Summary:
This patch modifies IncrementMemoryAddress to use a vscale
when calculating the new address if the data type is scalable.

Also adds tablegen patterns which match an extract_subvector
of a legal predicate type with zip1/zip2 instructions

Reviewers: sdesmalen, efriedma, david-arm

Reviewed By: efriedma, david-arm

Subscribers: tschuett, hiraditya, psnobl, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D83137