[all-commits] [llvm/llvm-project] 3ee580: [ARM][LowOverheadLoops] Handle reductions

[Sam Parker via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 3ee580d0176f69a9f724469660f1d1805e0b6a06
      https://github.com/llvm/llvm-project/commit/3ee580d0176f69a9f724469660f1d1805e0b6a06
  Author: Sam Parker <sam.parker at arm.com>
  Date:   2020-07-01 (Wed, 01 Jul 2020)

  Changed paths:
    M llvm/include/llvm/CodeGen/ReachingDefAnalysis.h
    M llvm/lib/CodeGen/ReachingDefAnalysis.cpp
    M llvm/lib/Target/ARM/ARMBaseInstrInfo.h
    M llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/reductions.ll
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/vector-arith-codegen.ll

  Log Message:
  -----------
  [ARM][LowOverheadLoops] Handle reductions

While validating live-out values, record instructions that look like
a reduction. This will comprise of a vector op (for now only vadd),
a vorr (vmov) which store the previous value of vadd and then a vpsel
in the exit block which is predicated upon a vctp. This vctp will
combine the last two iterations using the vmov and vadd into a vector
which can then be consumed by a vaddv.

Once we have determined that it's safe to perform tail-predication,
we need to change this sequence of instructions so that the
predication doesn't produce incorrect code. This involves changing
the register allocation of the vadd so it updates itself and the
predication on the final iteration will not update the falsely
predicated lanes. This mimics what the vmov, vctp and vpsel do and
so we then don't need any of those instructions.

Differential Revision: https://reviews.llvm.org/D75533