[all-commits] [llvm/llvm-project] ceb1b3: [mlir] [VectorOps] Add the ability to mark FP redu...

[Aart Bik via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: ceb1b327b53c82203deaa0b0ede3fb07ec8f823a
      https://github.com/llvm/llvm-project/commit/ceb1b327b53c82203deaa0b0ede3fb07ec8f823a
  Author: aartbik <ajcbik at google.com>
  Date:   2020-06-26 (Fri, 26 Jun 2020)

  Changed paths:
    M mlir/include/mlir/Conversion/Passes.td
    M mlir/include/mlir/Conversion/VectorToLLVM/ConvertVectorToLLVM.h
    M mlir/include/mlir/Dialect/LLVMIR/LLVMOpBase.td
    M mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp
    A mlir/test/Conversion/VectorToLLVM/vector-reduction-to-llvm.mlir
    M mlir/test/Conversion/VectorToLLVM/vector-to-llvm.mlir
    M mlir/test/Target/llvmir-intrinsics.mlir

  Log Message:
  -----------
  [mlir] [VectorOps] Add the ability to mark FP reductions with "reassociate" attribute

Rationale:
In general, passing "fastmath" from MLIR to LLVM backend is not supported, and even just providing such a feature for experimentation is under debate. However, passing fine-grained fastmath related attributes on individual operations is generally accepted. This CL introduces an option to instruct the vector-to-llvm lowering phase to annotate floating-point reductions with the "reassociate" fastmath attribute, which allows the LLVM backend to use SIMD implementations for such constructs. Oher lowering passes can start using this mechanism right away in cases where reassociation is allowed.

Benefit:
For some microbenchmarks on x86-avx2, speedups over 20 were observed for longer vector (due to cleaner, spill-free and SIMD exploiting code).

Usage:
mlir-opt --convert-vector-to-llvm="reassociate-fp-reductions"

Reviewed By: ftynse, mehdi_amini

Differential Revision: https://reviews.llvm.org/D82624