[all-commits] [llvm/llvm-project] a25593: [ARM] Supporting lowering of half-precision FP arg...

[Lucas Duarte Prates via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: a255931c40558edf87994c2a8ed9b274c3fbda30
      https://github.com/llvm/llvm-project/commit/a255931c40558edf87994c2a8ed9b274c3fbda30
  Author: Lucas Prates <lucas.prates at arm.com>
  Date:   2020-06-18 (Thu, 18 Jun 2020)

  Changed paths:
    M llvm/include/llvm/CodeGen/TargetLowering.h
    M llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
    M llvm/lib/Target/ARM/ARMCallLowering.cpp
    M llvm/lib/Target/ARM/ARMCallingConv.cpp
    M llvm/lib/Target/ARM/ARMCallingConv.td
    M llvm/lib/Target/ARM/ARMISelLowering.cpp
    M llvm/lib/Target/ARM/ARMISelLowering.h
    M llvm/test/CodeGen/ARM/GlobalISel/arm-unsupported.ll
    M llvm/test/CodeGen/ARM/fp16-args.ll
    M llvm/test/CodeGen/ARM/fp16-bitcast.ll
    M llvm/test/CodeGen/ARM/fp16-promote.ll
    M llvm/test/CodeGen/ARM/fp16-vminmaxnm-safe.ll
    M llvm/test/CodeGen/ARM/vecreduce-fadd-legalization-strict.ll
    M llvm/test/CodeGen/ARM/vecreduce-fmul-legalization-strict.ll
    M llvm/test/CodeGen/Thumb2/mve-shuffle.ll
    M llvm/test/CodeGen/Thumb2/mve-vdup.ll
    M llvm/test/CodeGen/Thumb2/mve-vecreduce-fminmax.ll

  Log Message:
  -----------
  [ARM] Supporting lowering of half-precision FP arguments and returns in AArch32's backend

Summary:
Half-precision floating point arguments and returns are currently
promoted to either float or int32 in clang's CodeGen and there's
no existing support for the lowering of `half` arguments and returns
from IR in AArch32's backend.

Such frontend coercions, implemented as coercion through memory
in clang, can cause a series of issues in argument lowering, as causing
arguments to be stored on the wrong bits on big-endian architectures
and incurring in missing overflow detections in the return of certain
functions.

This patch introduces the handling of half-precision arguments and returns in
the backend using the actual "half" type on the IR. Using the "half"
type the backend is able to properly enforce the AAPCS' directions for
those arguments, making sure they are stored on the proper bits of the
registers and performing the necessary floating point convertions.

Reviewers: rjmccall, olista01, asl, efriedma, ostannard, SjoerdMeijer

Reviewed By: ostannard

Subscribers: stuij, hiraditya, dmgreen, llvm-commits, chill, dnsampaio, danielkiss, kristof.beyls, cfe-commits

Tags: #clang, #llvm

Differential Revision: https://reviews.llvm.org/D75169