[all-commits] [llvm/llvm-project] 4612f3: [SVE] Add flag to specify SVE register size, using...

[paulwalker-arm via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 4612f391200d0b4e21bc040a098227d73679de53
      https://github.com/llvm/llvm-project/commit/4612f391200d0b4e21bc040a098227d73679de53
  Author: Paul Walker <paul.walker at arm.com>
  Date:   2020-06-18 (Thu, 18 Jun 2020)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.h
    M llvm/lib/Target/AArch64/AArch64Subtarget.cpp
    M llvm/lib/Target/AArch64/AArch64Subtarget.h
    M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
    A llvm/test/Analysis/CostModel/AArch64/sve-fixed-length.ll

  Log Message:
  -----------
  [SVE] Add flag to specify SVE register size, using this to calculate legal vector types.

Adds aarch64-sve-vector-bits-{min,max} to allow the size of SVE
data registers (in bits) to be specified. This allows the code
generator to make assumptions it normally couldn't. As a starting
point this information is used to mark fixed length vector types
that can fit within the specified size as legal.

Reviewers: rengolin, efriedma

Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D80384