[all-commits] [llvm/llvm-project] aab506: [AArch64] Fix BTI landing pad generation.

[Dani via All-commits]

  Branch: refs/heads/release/10.x
  Home:   https://github.com/llvm/llvm-project
  Commit: aab50695971617d37ad420b476671995f7078e79
      https://github.com/llvm/llvm-project/commit/aab50695971617d37ad420b476671995f7078e79
  Author: Daniel Kiss <daniel.kiss at arm.com>
  Date:   2020-06-16 (Tue, 16 Jun 2020)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64BranchTargets.cpp
    M llvm/test/CodeGen/AArch64/branch-target-enforcement.mir

  Log Message:
  -----------
  [AArch64] Fix BTI landing pad generation.

In some cases BTI landing pad is inserted even compatible instruction
was there already. Meta instruction does not count in this case
therefore skip them in the check for first instructions in the function.

Differential revision: https://reviews.llvm.org/D74492

(cherry picked from commit d5a186a60014dc1a8c979c978cb32aba7ecb9102)


  Commit: bf89c5aeb8915d488fa1c790e1b237b62a49c01f
      https://github.com/llvm/llvm-project/commit/bf89c5aeb8915d488fa1c790e1b237b62a49c01f
  Author: Daniel Kiss <daniel.kiss at arm.com>
  Date:   2020-06-16 (Tue, 16 Jun 2020)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64BranchTargets.cpp
    M llvm/test/CodeGen/AArch64/branch-target-enforcement.mir

  Log Message:
  -----------
  [AArch64] Fix BTI instruction emission.

Summary:
SCTLR_EL1.BT[01] controls the PACI[AB]SP compatibility with PBYTE 11
(see [1])
This bit will be set to zero so PACI[AB]SP are equal to BTI C
instruction only.

[1] https://developer.arm.com/docs/ddi0595/b/aarch64-system-registers/sctlr_el1

Reviewers: chill, tamas.petz, pbarrio, ostannard

Reviewed By: tamas.petz, ostannard

Subscribers: kristof.beyls, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D81746

(cherry picked from commit b8ae3fdfa579dbf366b1bb1cbfdbf8c51db7fa55)


Compare: https://github.com/llvm/llvm-project/compare/b980cc1cd320...bf89c5aeb891