[all-commits] [llvm/llvm-project] 8a397b: [AArch64][SVE] Add support for spilling/filling ZP...

[Cullen Rhodes via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 8a397b66b2c672999e9e6d63334d5bffd7db1a3f
      https://github.com/llvm/llvm-project/commit/8a397b66b2c672999e9e6d63334d5bffd7db1a3f
  Author: Cullen Rhodes <cullen.rhodes at arm.com>
  Date:   2020-05-28 (Thu, 28 May 2020)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
    M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
    M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
    M llvm/test/CodeGen/AArch64/spillfill-sve.mir

  Log Message:
  -----------
  [AArch64][SVE] Add support for spilling/filling ZPR2/3/4

Summary:
This patch enables the register allocator to spill/fill lists of 2, 3
and 4 SVE vectors registers to/from the stack. This is implemented with
pseudo instructions that get expanded to individual LDR_ZXI/STR_ZXI
instructions in AArch64ExpandPseudoInsts.

Patch by Sander de Smalen.

Reviewed By: efriedma

Differential Revision: https://reviews.llvm.org/D75988