[all-commits] [llvm/llvm-project] c010d4: [ARM] Improve codegen of volatile load/store of i64

[Victor Campos via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: c010d4d195506aaea76a1cc8afb5a6b5884dba44
      https://github.com/llvm/llvm-project/commit/c010d4d195506aaea76a1cc8afb5a6b5884dba44
  Author: Victor Campos <victor.campos at arm.com>
  Date:   2020-05-28 (Thu, 28 May 2020)

  Changed paths:
    M llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
    M llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
    M llvm/lib/Target/ARM/ARMISelLowering.cpp
    M llvm/lib/Target/ARM/ARMISelLowering.h
    M llvm/lib/Target/ARM/ARMInstrInfo.td
    M llvm/lib/Target/ARM/ARMInstrThumb2.td
    A llvm/test/CodeGen/ARM/i64_volatile_load_store.ll

  Log Message:
  -----------
  [ARM] Improve codegen of volatile load/store of i64

Summary:
Instead of generating two i32 instructions for each load or store of a volatile
i64 value (two LDRs or STRs), now emit LDRD/STRD.

These improvements cover architectures implementing ARMv5TE or Thumb-2.

The code generation explicitly deviates from using the register-offset
variant of LDRD/STRD. In this variant, the register allocated to the
register-offset cannot be reused in any of the remaining operands. Such
restriction seems to be non-trivial to implement in LLVM, thus it is
left as a to-do.

Differential Revision: https://reviews.llvm.org/D70072