[all-commits] [llvm/llvm-project] 07cd19: AMDGPU: Fix dropping MI flags when rewriting instr...

[Matt Arsenault via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 07cd19efa2a63b01aea9b516a7a003cb7f750a12
      https://github.com/llvm/llvm-project/commit/07cd19efa2a63b01aea9b516a7a003cb7f750a12
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2020-05-27 (Wed, 27 May 2020)

  Changed paths:
    M llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp
    M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
    M llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp
    M llvm/test/CodeGen/AMDGPU/dpp_combine.mir
    M llvm/test/CodeGen/AMDGPU/sdwa-ops.mir
    M llvm/test/CodeGen/AMDGPU/sdwa-peephole-instr.mir
    A llvm/test/CodeGen/AMDGPU/shrink-instructions-flags.mir

  Log Message:
  -----------
  AMDGPU: Fix dropping MI flags when rewriting instructions

All 3 passes that change instruction encodings were dropping MI
flags. This avoids scheduling regressions caused by setting
mayRaiseFPExceptions on FP instructions for non-strictfp functions.