[all-commits] [llvm/llvm-project] 2a5675: [MachineDebugify] Insert synthetic DBG_VALUE instr...
Vedant Kumar via All-commits
all-commits at lists.llvm.org
Wed Apr 22 17:05:11 PDT 2020
Branch: refs/heads/master
Home: https://github.com/llvm/llvm-project
Commit: 2a5675f11d3bc803a245c0e2a3b47491c8f8a065
https://github.com/llvm/llvm-project/commit/2a5675f11d3bc803a245c0e2a3b47491c8f8a065
Author: Vedant Kumar <vsk at apple.com>
Date: 2020-04-22 (Wed, 22 Apr 2020)
Changed paths:
M llvm/lib/CodeGen/MachineDebugify.cpp
M llvm/lib/Transforms/Utils/Debugify.cpp
A llvm/test/CodeGen/AArch64/GlobalISel/constant-mir-debugify.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi-insertpt-decrement.mir
A llvm/test/CodeGen/AArch64/GlobalISel/phi-mir-debugify.mir
A llvm/test/CodeGen/Generic/MIRDebugify/locations-and-values.mir
R llvm/test/CodeGen/Generic/MIRDebugify/locations.mir
M llvm/test/DebugInfo/debugify.ll
Log Message:
-----------
[MachineDebugify] Insert synthetic DBG_VALUE instructions
Summary:
Teach MachineDebugify how to insert DBG_VALUE instructions. This can
help find bugs causing CodeGen differences when debug info is present.
DBG_VALUE instructions are only emitted when -debugify-level is set to
locations+variables.
There is essentially no attempt made to match up DBG_VALUE register
operands with the local variables they ought to correspond to. I'm not
sure how to improve the situation. In some cases (MachineMemOperand?)
it's possible to find the IR instruction a MachineInstr corresponds to,
but in general this seems to call for "undoing" the work done by ISel.
Reviewers: dsanders, aprantl
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D78135
Commit: 2fa656cdfd836d5d3959466f05e44ae51bcded4e
https://github.com/llvm/llvm-project/commit/2fa656cdfd836d5d3959466f05e44ae51bcded4e
Author: Vedant Kumar <vsk at apple.com>
Date: 2020-04-22 (Wed, 22 Apr 2020)
Changed paths:
M llvm/lib/Transforms/Utils/Debugify.cpp
Log Message:
-----------
[Debugify] Do not require named metadata to be present when stripping
This allows -mir-strip-debug to be run without -debugify having run
before.
Commit: 6b58018c05f0aa6e8c648aef652fbf25793b9e3d
https://github.com/llvm/llvm-project/commit/6b58018c05f0aa6e8c648aef652fbf25793b9e3d
Author: Vedant Kumar <vsk at apple.com>
Date: 2020-04-22 (Wed, 22 Apr 2020)
Changed paths:
M llvm/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir
M llvm/test/CodeGen/ARM/fold-sext-sextload.ll
M llvm/test/CodeGen/ARM/fold-zext-zextload.ll
Log Message:
-----------
[ARM] Mark some tests as not safe for -debugify-and-strip-all, NFC
These tests contain debug instructions which get checked, so we can't
insert synthetic debug info and expect the tests to pass.
The rest of the ARM backend tests appear to be fair game.
Commit: 10ce1bc8d02738c20a7e6c49f51b28a26d93927f
https://github.com/llvm/llvm-project/commit/10ce1bc8d02738c20a7e6c49f51b28a26d93927f
Author: Vedant Kumar <vsk at apple.com>
Date: 2020-04-22 (Wed, 22 Apr 2020)
Changed paths:
M llvm/include/llvm/CodeGen/MachineBasicBlock.h
M llvm/lib/CodeGen/BranchFolding.cpp
M llvm/lib/CodeGen/MachineBasicBlock.cpp
M llvm/lib/CodeGen/RegisterPressure.cpp
M llvm/lib/Target/X86/X86AvoidStoreForwardingBlocks.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[MachineBasicBlock] Add helpers for skipping debug instructions [1/14]
Summary:
These helpers are exercised by follow-up commits in this patch series,
which is all about removing CodeGen differences with vs. without debug
info in the AArch64 backend.
Reviewers: fhahn, aprantl, jpaquette, paquette
Subscribers: kristof.beyls, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D78260
Commit: 5bae277584935ad9c5a545ac3c5ac8dd98457c67
https://github.com/llvm/llvm-project/commit/5bae277584935ad9c5a545ac3c5ac8dd98457c67
Author: Vedant Kumar <vsk at apple.com>
Date: 2020-04-22 (Wed, 22 Apr 2020)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir
Log Message:
-----------
[GISel][RegBankSelect] Hide assertion failure from LLT::getScalarSizeInBits [2/14]
Summary:
It looks like RegBankSelect can try to assign a bank based on a
DBG_VALUE instead of ignoring it. This eventually leads to an assert
in AArch64RegisterBankInfo::getInstrMapping because there is some info
missing from the DBG_VALUE MachineOperand (I see: `Assertion failed:
(RawData != 0 && "Invalid Type"), function getScalarSizeInBits`).
I'm not 100% sure it's safe to insert DBG_VALUE instructions right
before RegBankSelect (that's what -debugify-and-strip-all-safe is
doing). Any advice appreciated.
Depends on D78135.
Reviewers: ab, qcolombet, dsanders, aprantl
Subscribers: kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D78137
Commit: 5c04274dab4858180d756329d11499df247e9d2d
https://github.com/llvm/llvm-project/commit/5c04274dab4858180d756329d11499df247e9d2d
Author: Vedant Kumar <vsk at apple.com>
Date: 2020-04-22 (Wed, 22 Apr 2020)
Changed paths:
M llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/combiner-load-store-indexing.ll
Log Message:
-----------
[GIsel][CombinerHelper] Don't consider debug insts in dominance queries [3/14]
Summary:
This fixes several issues where the presence of debug instructions could
disable certain combines, due to dominance queries finding uses/defs that
don't actually exist.
Reviewers: dsanders, fhahn, paquette, aemerson
Subscribers: hiraditya, arphaman, aprantl, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D78253
Commit: ba9db54505ed7ba18367d0f8810feac143e99958
https://github.com/llvm/llvm-project/commit/ba9db54505ed7ba18367d0f8810feac143e99958
Author: Vedant Kumar <vsk at apple.com>
Date: 2020-04-22 (Wed, 22 Apr 2020)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/combiner-load-store-indexing.ll
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-br.mir
Log Message:
-----------
[GIsel][CombinerHelper] Fix for missed ElideBrByInvertingCond/CombineIndexedLoadStore combines [4/14]
Summary:
Fix an issue which could result in ElideBrByInvertingCond or
CombineIndexedLoadStore being missed when debug info is present. In both
cases the fix is s/hasOneUse/hasOneNonDbgUse/.
Reviewers: aemerson, dsanders
Subscribers: hiraditya, aprantl, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D78254
Commit: f1a71b5949069315a7f530e989f863f9c19d59f8
https://github.com/llvm/llvm-project/commit/f1a71b5949069315a7f530e989f863f9c19d59f8
Author: Vedant Kumar <vsk at apple.com>
Date: 2020-04-22 (Wed, 22 Apr 2020)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-memcpy-et-al.mir
A llvm/test/CodeGen/AArch64/GlobalISel/legalize-memcpy-with-debug-info.mir
Log Message:
-----------
[GIsel][LegalizerHelper] Account for debug insts when creating mem libcalls [5/14]
Summary:
While lowering memory intrinsics, GIsel attempts to form a tail call to
a library routine.
There might be a DBG_LABEL or something after the intrinsic call,
though: in that case, GIsel should still be able to form the tail call,
and should also delete the debug insts after the tail call as the
transform makes them invalid.
Reviewers: dsanders, aemerson
Subscribers: hiraditya, aprantl, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D78335
Commit: 26271c83849ba05982963bf5e85e54fc0de1389a
https://github.com/llvm/llvm-project/commit/26271c83849ba05982963bf5e85e54fc0de1389a
Author: Vedant Kumar <vsk at apple.com>
Date: 2020-04-22 (Wed, 22 Apr 2020)
Changed paths:
M llvm/lib/CodeGen/PeepholeOptimizer.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/test/CodeGen/AArch64/arm64-arm64-dead-def-elimination-flag.ll
Log Message:
-----------
[AArch64InstrInfo] Ignore debug insts in canInstrSubstituteCmpInstr [6/14]
Summary:
Fix an issue where the presence of debug info could disable a peephole
optimization in optimizeCompareInstr due to canInstrSubstituteCmpInstr
returning the wrong result.
Depends on D78137.
Reviewers: t.p.northover, eastig, paquette
Subscribers: kristof.beyls, hiraditya, danielkiss, aprantl, llvm-commits, dsanders
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D78151
Commit: f0b52beef3e3fa5e99aa9fae962f9df0cdaf5f74
https://github.com/llvm/llvm-project/commit/f0b52beef3e3fa5e99aa9fae962f9df0cdaf5f74
Author: Vedant Kumar <vsk at apple.com>
Date: 2020-04-22 (Wed, 22 Apr 2020)
Changed paths:
M llvm/lib/CodeGen/PeepholeOptimizer.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/test/CodeGen/AArch64/arm64-csel.ll
Log Message:
-----------
[AArch64InstrInfo] Ignore debug insts in areCFlagsAccessedBetweenInstrs [7/14]
Summary:
Fix an issue where the presence of debug info could disable a peephole
optimization due to areCFlagsAccessedBetweenInstrs returning the wrong
result.
In test/CodeGen/AArch64/arm64-csel.ll, the issue was found in the
function @foo5, in which the first compare could successfully be
optimized but not the second.
Reviewers: t.p.northover, eastig, paquette
Subscribers: kristof.beyls, hiraditya, danielkiss, aprantl, dsanders, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D78157
Commit: b157974ab3527e35e509d5b8f8f0f0e4f98c4c65
https://github.com/llvm/llvm-project/commit/b157974ab3527e35e509d5b8f8f0f0e4f98c4c65
Author: Vedant Kumar <vsk at apple.com>
Date: 2020-04-22 (Wed, 22 Apr 2020)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp
M llvm/test/CodeGen/AArch64/arm64-ccmp.ll
Log Message:
-----------
[AArch64ConditionalCompares] Ignore debug insts in findConvertibleCompare [8/14]
Summary:
Fix an issue where the presence of debug info could disable the ccmp
optimization due to findConvertibleCompare failing too early (the error
is "Can't create ccmp with multiple uses", where the "use" is a
DBG_VALUE inst).
Depends on D78151.
Reviewers: t.p.northover, paquette, aemerson
Subscribers: kristof.beyls, hiraditya, danielkiss, aprantl, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D78156
Commit: 4a51b61cb32358b1bdf3b90dd5220e5a6c65c3af
https://github.com/llvm/llvm-project/commit/4a51b61cb32358b1bdf3b90dd5220e5a6c65c3af
Author: Vedant Kumar <vsk at apple.com>
Date: 2020-04-22 (Wed, 22 Apr 2020)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
M llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
M llvm/test/CodeGen/AArch64/addsub-shifted.ll
M llvm/test/CodeGen/AArch64/addsub_ext.ll
Log Message:
-----------
[AArch64] Clean up assorted usage of hasOneUse/use_instructions [9/14]
Summary:
Use the variants of these APIs which skip over debug instructions. This
is mostly a cleanup, but it does fix a debug-variance issue which causes
addsub-shifted.ll and addsub_ext.ll to fail when debug info is inserted
by -mir-debugify.
Reviewers: aemerson, paquette
Subscribers: kristof.beyls, hiraditya, jfb, danielkiss, llvm-commits, aprantl
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D78262
Commit: 78d69e97cc24ed61167600a117fd42d136a56dbf
https://github.com/llvm/llvm-project/commit/78d69e97cc24ed61167600a117fd42d136a56dbf
Author: Vedant Kumar <vsk at apple.com>
Date: 2020-04-22 (Wed, 22 Apr 2020)
Changed paths:
M llvm/lib/Target/AArch64/AArch64CondBrTuning.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.h
M llvm/test/CodeGen/AArch64/arm64-early-ifcvt.ll
M llvm/test/CodeGen/AArch64/arm64-shrink-wrapping.ll
M llvm/test/CodeGen/AArch64/cond-br-tuning.ll
Log Message:
-----------
[AArch64CondBrTuning] Ignore debug insts when scanning for NZCV clobbers [10/14]
Summary:
This fixes several instances in which condbr optimization was missed
due to a debug instruction appearing as a bogus NZCV clobber.
Reviewers: aemerson, paquette
Subscribers: kristof.beyls, hiraditya, jfb, danielkiss, aprantl, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D78264
Commit: bf4c70b355620fec56df5c22a5704dea1e5b3b54
https://github.com/llvm/llvm-project/commit/bf4c70b355620fec56df5c22a5704dea1e5b3b54
Author: Vedant Kumar <vsk at apple.com>
Date: 2020-04-22 (Wed, 22 Apr 2020)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ConditionOptimizer.cpp
M llvm/test/CodeGen/AArch64/combine-comparisons-by-cse.ll
Log Message:
-----------
[AArch64ConditionOptimizer] Fix missed optimization due to debug insts [11/14]
Summary:
The findSuitableCompare method can fail if debug instructions are
present in the MBB -- fix this by using helpers to skip over debug
insts.
Reviewers: aemerson, paquette
Subscribers: kristof.beyls, hiraditya, danielkiss, aprantl, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D78265
Commit: c2c2dc526a6592c3863ae2b3b6027c6f7c80fda3
https://github.com/llvm/llvm-project/commit/c2c2dc526a6592c3863ae2b3b6027c6f7c80fda3
Author: Vedant Kumar <vsk at apple.com>
Date: 2020-04-22 (Wed, 22 Apr 2020)
Changed paths:
M llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
A llvm/test/CodeGen/AArch64/ldst-opt-mte-with-dbg.mir
M llvm/test/CodeGen/AArch64/ldst-opt-mte.mir
Log Message:
-----------
[AArch64LoadStoreOptimizer] Skip debug insts during pattern matching [12/14]
Do not count the presence of debug insts against the limit set by
LdStLimit, and allow the optimizer to find matching insts by skipping
over debug insts.
Differential Revision: https://reviews.llvm.org/D78411
Commit: ff8c417d31f0e615a022225014a0f94f6a5c73d2
https://github.com/llvm/llvm-project/commit/ff8c417d31f0e615a022225014a0f94f6a5c73d2
Author: Vedant Kumar <vsk at apple.com>
Date: 2020-04-22 (Wed, 22 Apr 2020)
Changed paths:
M llvm/lib/Target/AArch64/AArch64PreLegalizerCombiner.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/combine-fconstant.mir
Log Message:
-----------
[AArch64PreLegalizerCombiner] Fix debug invariance issue in matchFConstantToConstant [13/14]
Fix an issue where the FConstantToConstant combine could fail if debug
instructions were present.
Commit: e0b60c6df2f17642f4e952ebe192d5f84520ed8a
https://github.com/llvm/llvm-project/commit/e0b60c6df2f17642f4e952ebe192d5f84520ed8a
Author: Vedant Kumar <vsk at apple.com>
Date: 2020-04-22 (Wed, 22 Apr 2020)
Changed paths:
M llvm/lib/Target/AArch64/AArch64CollectLOH.cpp
M llvm/test/CodeGen/AArch64/loh.mir
Log Message:
-----------
[AArch64CollectLOH] Debug insts should not break LOH collection [14/14]
Fix an issue where the presence of debug instructions could break
collection of linker optimization hints.
Compare: https://github.com/llvm/llvm-project/compare/b424b0bf731d...e0b60c6df2f1
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