[all-commits] [llvm/llvm-project] c697dd: [ARM] Make remaining MVE instruction predictable

[David Green via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: c697dd9ffdb14f08766c738eb28c377ee964937f
      https://github.com/llvm/llvm-project/commit/c697dd9ffdb14f08766c738eb28c377ee964937f
  Author: David Green <david.green at arm.com>
  Date:   2020-04-02 (Thu, 02 Apr 2020)

  Changed paths:
    M llvm/lib/Target/ARM/ARMInstrMVE.td
    M llvm/test/CodeGen/Thumb2/mve-vld3.ll
    M llvm/test/CodeGen/Thumb2/mve-vld4.ll
    M llvm/test/CodeGen/Thumb2/mve-vst3.ll
    M llvm/unittests/Target/ARM/MachineInstrTest.cpp

  Log Message:
  -----------
  [ARM] Make remaining MVE instruction predictable

The unpredictable/hasSideEffects flag is usually inferred by tablegen
from whether the instruction has a tablegen pattern (and that pattern
only has a single output instruction). Now that the MVE intrinsics are
all committed and producing code, the remaining instructions still
marked as unpredictable need to be specially handled. This adds the flag
directly to instructions that need it, notably the V*MLAL instructions
and some of the MOV's.

Differential Revision: https://reviews.llvm.org/D76910


  Commit: fbd53ffc3ad97bf39cc1420ac160f402f6a0c935
      https://github.com/llvm/llvm-project/commit/fbd53ffc3ad97bf39cc1420ac160f402f6a0c935
  Author: David Green <david.green at arm.com>
  Date:   2020-04-02 (Thu, 02 Apr 2020)

  Changed paths:
    M llvm/lib/Target/ARM/ARMISelLowering.cpp
    M llvm/lib/Target/ARM/ARMInstrInfo.td
    M llvm/lib/Target/ARM/ARMInstrMVE.td
    M llvm/lib/Target/ARM/ARMInstrNEON.td
    M llvm/test/CodeGen/Thumb2/mve-vecreduce-mla.ll
    M llvm/test/CodeGen/Thumb2/mve-vmull-loop.ll
    M llvm/test/CodeGen/Thumb2/mve-vmull.ll

  Log Message:
  -----------
  [ARM] MVE VMULL patterns

This adds MVE vmull patterns, which are conceptually the same as
mul(vmovl, vmovl), and so the tablegen patterns follow the same
structure.

For i8 and i16 this is simple enough, but in the i32 version the
multiply (in 64bits) is illegal, meaning we need to catch the pattern
earlier in a dag fold. Because bitcasts are involved in the zext
versions and the patterns are a little different in little and big
endian. I have only added little endian support in this patch.

Differential Revision: https://reviews.llvm.org/D76740


Compare: https://github.com/llvm/llvm-project/compare/62be83463a37...fbd53ffc3ad9