[all-commits] [llvm/llvm-project] bd12ec: [AMDGPU] Fix PC register mapping in wave32 mode

[Scott Linder via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: bd12ecb88f0a3b9b3ca60814d20a7e9b0933f2ec
      https://github.com/llvm/llvm-project/commit/bd12ecb88f0a3b9b3ca60814d20a7e9b0933f2ec
  Author: Scott Linder <Scott.Linder at amd.com>
  Date:   2020-03-26 (Thu, 26 Mar 2020)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
    M llvm/unittests/MC/AMDGPU/DwarfRegMappings.cpp
    M llvm/unittests/Target/AMDGPU/DwarfRegMappings.cpp

  Log Message:
  -----------
  [AMDGPU] Fix PC register mapping in wave32 mode

Summary:
The PC_32 DWARF register is for a 32-bit process address space which we
don't implement in AMDGCN; another way of putting this is that the size
of the PC register is not a function of the wavefront size. If we ever
implement a 32-bit process address space we will need to add two more
DwarfFlavours i.e. we will need to represent the product of (wave32,
wave64) x (64-bit address space, 32-bit address space).

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D76732