[all-commits] [llvm/llvm-project] 6e34e7: [AMDGPU] Enable divergence driven ISel for ADD/SU...

[alex-t via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 6e34e71869ab57ee33cb361426789ee85e1cde87
      https://github.com/llvm/llvm-project/commit/6e34e71869ab57ee33cb361426789ee85e1cde87
  Author: alex-t <alexander.timofeev at amd.com>
  Date:   2020-03-20 (Fri, 20 Mar 2020)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
    M llvm/test/CodeGen/AMDGPU/bypass-div.ll
    M llvm/test/CodeGen/AMDGPU/sdiv64.ll
    M llvm/test/CodeGen/AMDGPU/srem64.ll
    M llvm/test/CodeGen/AMDGPU/udiv64.ll
    M llvm/test/CodeGen/AMDGPU/urem64.ll

  Log Message:
  -----------
   [AMDGPU] Enable divergence driven ISel for ADD/SUB i64

Summary:
Currently we custom select add/sub with carry out to scalar form relying on later replacing them to vector form if necessary.
This change enables custom selection code to take the divergence of adde/addc SDNodes into account and select the appropriate form in one step.

Reviewers: arsenm, vpykhtin, rampitec

Reviewed By: arsenm, vpykhtin

Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, kerbowa

Differential Revision: https://reviews.llvm.org/D76371