[all-commits] [llvm/llvm-project] 7a85e3: [ARM, CDE] Implement GPR CDE intrinsics

Fri Mar 20 07:02:36 PDT 2020

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 7a85e3585ec59b1bfe3b08072ff042af80d07f22
      https://github.com/llvm/llvm-project/commit/7a85e3585ec59b1bfe3b08072ff042af80d07f22
  Author: Mikhail Maltsev <mikhail.maltsev at arm.com>
  Date:   2020-03-20 (Fri, 20 Mar 2020)

  Changed paths:
    M clang/include/clang/Basic/arm_cde.td
    M clang/test/CodeGen/arm-cde-gpr.c
    M clang/test/Sema/arm-cde-immediates.c
    M llvm/include/llvm/IR/IntrinsicsARM.td
    M llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
    M llvm/lib/Target/ARM/ARMInstrCDE.td
    A llvm/test/CodeGen/Thumb2/cde-gpr.ll

  Log Message:
  -----------
  [ARM,CDE] Implement GPR CDE intrinsics

Summary:
This change implements ACLE CDE intrinsics that translate to
instructions working with general-purpose registers.

The specification is available at
https://static.docs.arm.com/101028/0010/ACLE_2019Q4_release-0010.pdf

Each ACLE intrinsic gets a corresponding LLVM IR intrinsic (because
they have distinct function prototypes). Dual-register operands are
represented as pairs of i32 values. Because of this the instruction
selection for these intrinsics cannot be represented as TableGen
patterns and requires custom C++ code.

Reviewers: simon_tatham, MarkMurrayARM, dmgreen, ostannard

Reviewed By: MarkMurrayARM

Subscribers: kristof.beyls, hiraditya, danielkiss, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D76296

  Commit: d22e66171251cd3dd07507912189aa814a419678
      https://github.com/llvm/llvm-project/commit/d22e66171251cd3dd07507912189aa814a419678
  Author: Mikhail Maltsev <mikhail.maltsev at arm.com>
  Date:   2020-03-20 (Fri, 20 Mar 2020)

  Changed paths:
    M clang/include/clang/Basic/arm_cde.td
    A clang/test/CodeGen/arm-cde-vfp.c
    M clang/test/Sema/arm-cde-immediates.c
    M clang/utils/TableGen/MveEmitter.cpp
    M llvm/include/llvm/IR/IntrinsicsARM.td
    M llvm/lib/Target/ARM/ARMInstrCDE.td
    A llvm/test/CodeGen/Thumb2/cde-vfp.ll

  Log Message:
  -----------
  [ARM,CDE] Implement CDE S and D-register intrinsics

Summary:
This patch implements the following ACLE intrinsics:

  uint32_t __arm_vcx1_u32(int coproc, uint32_t imm);
  uint32_t __arm_vcx1a_u32(int coproc, uint32_t acc, uint32_t imm);
  uint32_t __arm_vcx2_u32(int coproc, uint32_t n, uint32_t imm);
  uint32_t __arm_vcx2a_u32(int coproc, uint32_t acc, uint32_t n, uint32_t imm);
  uint32_t __arm_vcx3_u32(int coproc, uint32_t n, uint32_t m, uint32_t imm);
  uint32_t __arm_vcx3a_u32(int coproc, uint32_t acc, uint32_t n, uint32_t m, uint32_t imm);

  uint64_t __arm_vcx1d_u64(int coproc, uint32_t imm);
  uint64_t __arm_vcx1da_u64(int coproc, uint64_t acc, uint32_t imm);
  uint64_t __arm_vcx2d_u64(int coproc, uint64_t m, uint32_t imm);
  uint64_t __arm_vcx2da_u64(int coproc, uint64_t acc, uint64_t m, uint32_t imm);
  uint64_t __arm_vcx3d_u64(int coproc, uint64_t n, uint64_t m, uint32_t imm);
  uint64_t __arm_vcx3da_u64(int coproc, uint64_t acc, uint64_t n, uint64_t m, uint32_t imm);

Since the semantics of CDE instructions is opaque to the compiler, the
ACLE intrinsics require dedicated LLVM IR intrinsics. The 64-bit and
32-bit variants share the same IR intrinsic.

Reviewers: simon_tatham, MarkMurrayARM, ostannard, dmgreen

Reviewed By: MarkMurrayARM

Subscribers: kristof.beyls, hiraditya, danielkiss, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D76298

  Commit: 969034b86037d3c1daf725aef13ba16424f92fe1
      https://github.com/llvm/llvm-project/commit/969034b86037d3c1daf725aef13ba16424f92fe1
  Author: Mikhail Maltsev <mikhail.maltsev at arm.com>
  Date:   2020-03-20 (Fri, 20 Mar 2020)

  Changed paths:
    M clang/include/clang/Basic/arm_cde.td
    A clang/test/CodeGen/arm-cde-vec.c
    M clang/test/Sema/arm-cde-immediates.c
    M clang/utils/TableGen/MveEmitter.cpp
    M llvm/include/llvm/IR/IntrinsicsARM.td
    M llvm/lib/Target/ARM/ARMInstrCDE.td
    A llvm/test/CodeGen/Thumb2/cde-vec.ll

  Log Message:
  -----------
  [ARM,CDE] Implement CDE unpredicated Q-register intrinsics

Summary:
This patch implements the following intrinsics:

  uint8x16_t __arm_vcx1q_u8 (int coproc, uint32_t imm);
  T __arm_vcx1qa(int coproc, T acc, uint32_t imm);
  T __arm_vcx2q(int coproc, T n, uint32_t imm);
  uint8x16_t __arm_vcx2q_u8(int coproc, T n, uint32_t imm);
  T __arm_vcx2qa(int coproc, T acc, U n, uint32_t imm);
  T __arm_vcx3q(int coproc, T n, U m, uint32_t imm);
  uint8x16_t __arm_vcx3q_u8(int coproc, T n, U m, uint32_t imm);
  T __arm_vcx3qa(int coproc, T acc, U n, V m, uint32_t imm);

Most of them are polymorphic. Furthermore, some intrinsics are
polymorphic by 2 or 3 parameter types, such polymorphism is not
supported by the existing MVE/CDE tablegen backends, also we don't
really want to have a combinatorial explosion caused by 1000 different
combinations of 3 vector types. Because of this some intrinsics are
implemented as macros involving a cast of the polymorphic arguments to
uint8x16_t.

The IR intrinsics are even more restricted in terms of types: all MVE
vectors are cast to v16i8.

Reviewers: simon_tatham, MarkMurrayARM, dmgreen, ostannard

Reviewed By: MarkMurrayARM

Subscribers: kristof.beyls, hiraditya, danielkiss, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D76299

  Commit: 6ae3eff8baaca95752b1ec9732c605b3d4e8d630
      https://github.com/llvm/llvm-project/commit/6ae3eff8baaca95752b1ec9732c605b3d4e8d630
  Author: Mikhail Maltsev <mikhail.maltsev at arm.com>
  Date:   2020-03-20 (Fri, 20 Mar 2020)

  Changed paths:
    M clang/include/clang/Basic/arm_cde.td
    A clang/test/CodeGen/arm-cde-reinterpret.c

  Log Message:
  -----------
  [ARM,CDE] Implement CDE vreinterpret intrinsics

Summary:
This patch implements the following CDE intrinsics:

  int8x16_t __arm_vreinterpretq_s8_u8 (uint8x16_t in);
  uint16x8_t __arm_vreinterpretq_u16_u8 (uint8x16_t in);
  int16x8_t __arm_vreinterpretq_s16_u8 (uint8x16_t in);
  uint32x4_t __arm_vreinterpretq_u32_u8 (uint8x16_t in);
  int32x4_t __arm_vreinterpretq_s32_u8 (uint8x16_t in);
  uint64x2_t __arm_vreinterpretq_u64_u8 (uint8x16_t in);
  int64x2_t __arm_vreinterpretq_s64_u8 (uint8x16_t in);
  float16x8_t __arm_vreinterpretq_f16_u8 (uint8x16_t in);
  float32x4_t __arm_vreinterpretq_f32_u8 (uint8x16_t in);

These intrinsics are header-only because they reuse the existing
MVE vreinterpret clang built-ins.

This set is slightly different from the published specification
(see https://static.docs.arm.com/101028/0010/ACLE_2019Q4_release-0010.pdf):
it includes

  int8x16_t __arm_vreinterpretq_s8_u8 (uint8x16_t in);

which was unintentionally ommitted from the spec, and
does not include

  float64x2_t __arm_vreinterpretq_f64_u8 (uint8x16_t in);

The float64x2_t type requires additional implementation
effort, and we are not including it yet.

Reviewers: simon_tatham, MarkMurrayARM, dmgreen, ostannard

Reviewed By: MarkMurrayARM

Subscribers: kristof.beyls, danielkiss, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D76300

Compare: https://github.com/llvm/llvm-project/compare/ece6cf0fa566...6ae3eff8baac