[all-commits] [llvm/llvm-project] 7049cf: [BranchAlign] Fix bug w/nop padding for SS manipul...

[Philip Reames via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 7049cf6496c9aa8e355345a3fbea30861e4d2da8
      https://github.com/llvm/llvm-project/commit/7049cf6496c9aa8e355345a3fbea30861e4d2da8
  Author: Philip Reames <listmail at philipreames.com>
  Date:   2020-03-02 (Mon, 02 Mar 2020)

  Changed paths:
    M llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
    A llvm/test/MC/X86/align-branch-64-system.s

  Log Message:
  -----------
  [BranchAlign] Fix bug w/nop padding for SS manipulation

X86 has several instructions which are documented as enabling interrupts exactly one instruction *after* the one which changes the SS segment register. Inserting a nop between these two instructions allows an interrupt to arrive before the execution of the following instruction which changes semantic behaviour.

The list of instructions is documented in "Table 24-3. Format of Interruptibility State" in Volume 3c of the Intel manual. They basically all come down to different ways to write to the SS register.

Differential Revision: https://reviews.llvm.org/D75359