[all-commits] [llvm/llvm-project] 9897da: Update LSR's logic that identifies a post-incremen...

[sgundapa via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 9897daa6bfcce044473f63e12492ec7748e8eb62
      https://github.com/llvm/llvm-project/commit/9897daa6bfcce044473f63e12492ec7748e8eb62
  Author: Sumanth Gundapaneni <sgundapa at quicinc.com>
  Date:   2020-03-02 (Mon, 02 Mar 2020)

  Changed paths:
    M llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
    M llvm/test/CodeGen/Hexagon/addrmode-align.ll
    A llvm/test/CodeGen/Hexagon/lsr-postinc-nested-loop.ll
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-float-loops.ll
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-tail-data-types.ll

  Log Message:
  -----------
  Update LSR's logic that identifies a post-increment SCEV value.

One of the checks has been removed as it seem invalid.
The LoopStep size is always almost a 32-bit.

Differential Revision: https://reviews.llvm.org/D75079