[all-commits] [llvm/llvm-project] e7a184: [X86] Use movlps for i64 atomic stores on 32-targe...

[topperc via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: e7a184fc7c044b883ab782fa05e56f873050bd72
      https://github.com/llvm/llvm-project/commit/e7a184fc7c044b883ab782fa05e56f873050bd72
  Author: Craig Topper <craig.topper at gmail.com>
  Date:   2020-02-22 (Sat, 22 Feb 2020)

  Changed paths:
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/test/CodeGen/X86/atomic-fp.ll
    M llvm/test/CodeGen/X86/atomic-non-integer.ll

  Log Message:
  -----------
  [X86] Use movlps for i64 atomic stores on 32-targets with sse1.

This is similar to using movd which we do for sse2 targets.

I've added a DAG combine for VEXTRACT_STORE to use SimplifyDemandedVectorElts
to clean up some artifacts from type legalization.


  Commit: bdb1729c8347c2b7d932976f8588e524b4f7b8d5
      https://github.com/llvm/llvm-project/commit/bdb1729c8347c2b7d932976f8588e524b4f7b8d5
  Author: Craig Topper <craig.topper at gmail.com>
  Date:   2020-02-22 (Sat, 22 Feb 2020)

  Changed paths:
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/test/CodeGen/X86/atomic-fp.ll
    M llvm/test/CodeGen/X86/atomic-non-integer.ll
    M llvm/test/CodeGen/X86/merge-consecutive-loads-128.ll

  Log Message:
  -----------
  [X86] Teach EltsFromConsecutiveLoads that it's ok to form a v4f32 VZEXT_LOAD with a 64 bit memory size on SSE1 targets.

We can use MOVLPS which will load 64 bits, but we need a v4f32
result type. We already have isel patterns for this.

The code here is a little hacky. We can probably improve it with
more isel patterns.


Compare: https://github.com/llvm/llvm-project/compare/1df947ab403a...bdb1729c8347