[all-commits] [llvm/llvm-project] 72eef8: AMDGPU/GlobalISel: Select G_SHUFFLE_VECTOR
Matt Arsenault via All-commits
all-commits at lists.llvm.org
Fri Feb 21 10:35:47 PST 2020
Branch: refs/heads/master
Home: https://github.com/llvm/llvm-project
Commit: 72eef820d528ab93982e54cd49c44fabf20e83a5
https://github.com/llvm/llvm-project/commit/72eef820d528ab93982e54cd49c44fabf20e83a5
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2020-02-21 (Fri, 21 Feb 2020)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.cpp
M llvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.h
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
A llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shuffle-vector.v2s16.mir
Log Message:
-----------
AMDGPU/GlobalISel: Select G_SHUFFLE_VECTOR
G_SHUFFLE_VECTOR is legal since it theoretically may help match op_sel
for VOP3P instructions. Expand it in some other way in case it doesn't
fold into the use instructions.
Commit: dfce5fd50a00110890ad95dacca75886c6fd456d
https://github.com/llvm/llvm-project/commit/dfce5fd50a00110890ad95dacca75886c6fd456d
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2020-02-21 (Fri, 21 Feb 2020)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUGISel.td
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
A llvm/test/CodeGen/AMDGPU/GlobalISel/fmul.v2f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.v2s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcanonicalize.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.v2s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum.v2s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum-ieee.v2s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum.v2s16.mir
A llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmul.v2s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.v2s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.v2s16.mir
Log Message:
-----------
AMDGPU/GlobalISel: Select VOP3P instructions
This only handles the basic cases. More work is needed to make better
use of op_sel.
Commit: 4c1c9422a3adab64433b8fde31f1ac346459b491
https://github.com/llvm/llvm-project/commit/4c1c9422a3adab64433b8fde31f1ac346459b491
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2020-02-21 (Fri, 21 Feb 2020)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
A llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.fdot2.ll
Log Message:
-----------
AMDGPU/GlobalISel: Select llvm.amdgcn.fdot2
I'm slighly worried about the generated checks, since they won't catch
incorrect modifiers being added at the end of the line.
Commit: db06870dbd5e85acbd39bb8dc3b2e1c751904f86
https://github.com/llvm/llvm-project/commit/db06870dbd5e85acbd39bb8dc3b2e1c751904f86
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2020-02-21 (Fri, 21 Feb 2020)
Changed paths:
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
A llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sdot2.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sdot4.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sdot8.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot2.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot4.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot8.ll
Log Message:
-----------
AMDGPU: Move dot intrinsic patterns to instruction def
I tried to use some of the new tablegen features to avoid creating
different operand list permutations, but I still don't see a way to
programmatically build a source pattern dag.
Also add GlobalISel tests, which now all import successfully.
Some of the fneg fold tests are incorrect, which need to be fixed in a
future commit
Compare: https://github.com/llvm/llvm-project/compare/1723f219939e...db06870dbd5e
More information about the All-commits
mailing list