[all-commits] [llvm/llvm-project] 5cee34: [PowerPC][Future] Add prefixed instruction paddi t...

[Victor Huang via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 5cee34013cfd4edea0041bc0b73121cc4ad76ccf
      https://github.com/llvm/llvm-project/commit/5cee34013cfd4edea0041bc0b73121cc4ad76ccf
  Author: Victor Huang <wei.huang at ibm.com>
  Date:   2020-01-24 (Fri, 24 Jan 2020)

  Changed paths:
    M llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
    M llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
    M llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
    M llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.h
    M llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
    M llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.h
    M llvm/lib/Target/PowerPC/PPC.td
    M llvm/lib/Target/PowerPC/PPCInstrFormats.td
    M llvm/lib/Target/PowerPC/PPCInstrInfo.h
    M llvm/lib/Target/PowerPC/PPCInstrInfo.td
    A llvm/lib/Target/PowerPC/PPCInstrPrefix.td
    M llvm/lib/Target/PowerPC/PPCScheduleP9.td
    M llvm/lib/Target/PowerPC/PPCSubtarget.cpp
    M llvm/lib/Target/PowerPC/PPCSubtarget.h
    A llvm/test/CodeGen/PowerPC/future-check-features.ll
    A llvm/test/MC/Disassembler/PowerPC/future-invalid.txt
    A llvm/test/MC/Disassembler/PowerPC/futureinsts.txt
    A llvm/test/MC/PowerPC/future.s

  Log Message:
  -----------
  [PowerPC][Future] Add prefixed instruction paddi to future CPU

Future CPU will include support for prefixed instructions.
These prefixed instructions are formed by a 4 byte prefix
immediately followed by a 4 byte instruction effectively
making an 8 byte instruction. The new instruction paddi
is a prefixed form of addi.

This patch adds paddi and all of the support required
for that instruction. The majority of the patch deals with
supporting the new prefixed instructions. The addition of
paddi is mainly to allow for testing.

Differential Revision: https://reviews.llvm.org/D72569