[all-commits] [llvm/llvm-project] e0f0d0: [MachineScheduler] Allow clustering mem ops with c...

[jayfoad via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: e0f0d0e55cc7d389ad0692fbc9678e7895978355
      https://github.com/llvm/llvm-project/commit/e0f0d0e55cc7d389ad0692fbc9678e7895978355
  Author: Jay Foad <jay.foad at amd.com>
  Date:   2020-01-22 (Wed, 22 Jan 2020)

  Changed paths:
    M llvm/include/llvm/CodeGen/TargetInstrInfo.h
    M llvm/lib/CodeGen/MachineScheduler.cpp
    M llvm/lib/CodeGen/TargetInstrInfo.cpp
    M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
    M llvm/lib/Target/AArch64/AArch64InstrInfo.h
    M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
    M llvm/lib/Target/AMDGPU/SIInstrInfo.h
    M llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
    M llvm/lib/Target/Hexagon/HexagonInstrInfo.h
    M llvm/lib/Target/Lanai/LanaiInstrInfo.cpp
    M llvm/lib/Target/Lanai/LanaiInstrInfo.h
    M llvm/lib/Target/X86/X86InstrInfo.cpp
    M llvm/lib/Target/X86/X86InstrInfo.h

  Log Message:
  -----------
  [MachineScheduler] Allow clustering mem ops with complex addresses

The generic BaseMemOpClusterMutation calls into TargetInstrInfo to
analyze the address of each load/store instruction, and again to decide
whether two instructions should be clustered. Previously this had to
represent each address as a single base operand plus a constant byte
offset. This patch extends it to support any number of base operands.

The old target hook getMemOperandWithOffset is now a convenience
function for callers that are only prepared to handle a single base
operand. It calls the new more general target hook
getMemOperandsWithOffset.

The only requirements for the base operands returned by
getMemOperandsWithOffset are:
- they can be sorted by MemOpInfo::Compare, such that clusterable ops
  get sorted next to each other, and
- shouldClusterMemOps knows what they mean.

One simple follow-on is to enable clustering of AMDGPU FLAT instructions
with both vaddr and saddr (base register + offset register). I've left
a FIXME in the code for this case.

Differential Revision: https://reviews.llvm.org/D71655