[all-commits] [llvm/llvm-project] 9c9286: AMDGPU: Fix interaction of tfe and d16

[Matt Arsenault via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 9c928649a085646c4c779bac095643b50b464d83
      https://github.com/llvm/llvm-project/commit/9c928649a085646c4c779bac095643b50b464d83
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2020-01-22 (Wed, 22 Jan 2020)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
    A llvm/test/CodeGen/AMDGPU/image-load-d16-tfe.ll

  Log Message:
  -----------
  AMDGPU: Fix interaction of tfe and d16

This using the wrong result register, and dropping the result entirely
for v2f16. This would fail to select on the scalar case. I believe it
was also mishandling packed/unpacked subtargets.


  Commit: a722cbf77cc638064592c508ea0c1be13775ee31
      https://github.com/llvm/llvm-project/commit/a722cbf77cc638064592c508ea0c1be13775ee31
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2020-01-22 (Wed, 22 Jan 2020)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUGISel.td
    M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
    M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
    M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
    M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
    M llvm/lib/Target/AMDGPU/SIInstructions.td
    A llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.atomic.dec.ll
    A llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.atomic.inc.ll
    R llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.atomic.dec.mir
    R llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.atomic.inc.mir

  Log Message:
  -----------
  AMDGPU/GlobalISel: Handle atomic_inc/atomic_dec

The intermediate instruction drops the extra volatile argument. We are
missing an atomic ordering on these.


  Commit: 70096ca111ee2848fb2e29a7cb3e4fb7e3ba9ef9
      https://github.com/llvm/llvm-project/commit/70096ca111ee2848fb2e29a7cb3e4fb7e3ba9ef9
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2020-01-22 (Wed, 22 Jan 2020)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
    A llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.fmul.legacy.mir

  Log Message:
  -----------
  AMDGPU/GlobalISel: Fix RegbankSelect for llvm.amdgcn.fmul.legacy


Compare: https://github.com/llvm/llvm-project/compare/4481eefbe842...70096ca111ee